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74F402 Serial Data Polynomial Generator/Checker
April 1988 Revised August 1999
74F402 Serial Data Polynomial Generator/Checker
General Description
The 74F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the 74F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems. A 4-bit control input selects one-of-six generator polynomials. The list of polynomials includes CRC16, CRC-CCITT and Ethernet(R), as well as three other standard polynomials (56th order, 48th order, 32nd order). Individual clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. The CWG Control input inhibits feedback during check word transmission. The 74F402 is compatible with FAST(R) devices and with all TTL families.
Features
s Guaranteed 30 MHz data rate s Six selectable polynomials s Other polynomials available s Separate preset and clear controls s Expandable s Automatic right justification s Error output open collector s Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems
Ordering Code:
Order Number 74F402PC Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
FAST(R) is a registered trademark of Fairchild Semiconductor Corporation. Ethernet(R) is a registered trademark of Xerox Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS009535
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74F402
Unit Loading/Fan Out
Pin Names S0-S3 CWG D/CW D ER RO CP SEI RFB MR P
Note 1: Open Collector
Description Polynomial Select Inputs Check Word Generate Input Serial Data/Check Word Data Input Error Output Register Output Clock Pulse Serial Expansion Input Register Feedback Master Reset Preset
U.L. HIGH/LOW 1.0/0.67 1.0/0.67 285(100)/13.3(6.7) 1.0/0.67 (Note 1) /26.7(13.3) 285(100)/13.3(6.7) 1.0/0.67 1.0/0.67 1.0/0.67 1.0/0.67 1.0/0.67
Input IIH/IIL Output IOH/IOL 20 A/-0.4 mA 20 A/-0.4 mA -5.7 mA(-2 mA)/8 mA (4 mA) 20 A/-0.4 mA (Note 1) /16 mA (8 mA) -5.7 mA(-2 mA)/8 mA (4 mA) 20 A/-0.4 mA 20 A/-0.4 mA 20 A/-0.4 mA 20 A/-0.4 mA 20 A/-0.4 mA
Functional Description
The 74F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This division results in a remainder (or residue) which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F402 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1, S2 and S3. The 74F402 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram. The polynomial control code presented at inputs S0, S1, S2 and S3 is decoded by the ROM, selecting the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data Inputs (D), using the LOW-to-HIGH transition of the Clock Input (CP). This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB), and controls the XOR gates. The Check Word Generate (CWG) must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the register(s) and appended to the data bits (no external gating is needed). To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid after the last check bit has been entered into the 'F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial (see Applications paragraph). If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOWto-HIGH transition of CP or until the device has been preset or reset. A HIGH on the Master Reset Input (MR) asynchronously clears the entire register. A LOW on the Preset Input (P) asynchronously sets the entire register with the exception of: 1. The Ethernet residue selection, in which the registers containing the non-zero residue are cleared; 2. The 56th order polynomial, in which the 8 least significant register bits of the least significant device are cleared; and, 3. Register S = 0, in which all bits are cleared.
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TABLE 1. Hex 0 C D E F 7 B 3 2 4 8 5 9 1 6 A Select Code S3 L H H H H L H L L L H L H L L H S2 L H H H H H L L L H L H L L H L S1 L L L H H H H H H L L L L L H H S0 L L H L H H H H L L L H H H L L 0 X32+X26+X23+X22+X16+ X12+X11+X10+X8+X7+X5+X4+X2+X+1 X32+X31+X27+X26+X25+X19+X16+ X15+X13+X12+X11+X9+X7+X6+X5+X4+X2+X+1 X16+X15+X2+1 X16+X12+X5+1 X56+X55+X49+X45+X41+ X39+X38+X37+X36+X31+ X22+X19+X17+X16+X15+X14+X12+X11+X9+ X5+X+1 X48+X36+X35+ X23+X21+ X15+X13+X8+X2+1 X32+X23+X21+ X11+X2+1 48th Order 32nd Order 56th Order Polynomial Remarks S=0 Ethernet Polynomial Ethernet Residue CRC-16 CRC-CCITT
Block Diagram
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TABLE 2. Select Code 0 C D E F 7 B 3 2 4 8 5 9 1 6 A P3 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 P2 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 P1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 P0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 C2 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 C1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 C0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 32nd Order 48th Order 56th Order Polynomial S=0 Ethernet Polynomial Ethernet Residue CRC-16 CRC-CCITT
Applications
In addition to polynomial selection there are four other capabilities provided for in the 74F402 ROM. The first is set or clear selectability. The sixteen internal registers have the capability to be either set or cleared when P is brought LOW. This set or clear capability is done in four groups of 4 (see Table 2, P0-P3). The second ROM capability (C0) is in determining the polarity of the check word. As is the case with the Ethernet polynomial the check word can be inverted when it is appended to the data stream or as is the case with the other polynomials, the residue is appended with no inversion. Thirdly, the ROM contains a bit (C1) which is used to select the RFB input instead of the SEI input to be fed into the LSB. This is used when the polynomial selected is actually a residue (least significant) stored in the ROM which indicates whether the selected location is a polynomial or a residue. If the latter, then it inhibits the RFB input. As mentioned previously, upon a successful data transmission, the CRC register has a zero residue. There is an exception to this, however, with respect to the Ethernet polynomial. This polynomial, upon a successful data transmission, has a non-zero residue in the CRC register (C7 04 DD 7B)16. In order to provide a no-error indication, two ROM locations have been preloaded with the residue so that by selecting these locations and clocking the device one additional time, after the last check bit has been entered, will result in zeroing the CRC register. In this manner a no-error indication is achieved. With the present mix of polynomials, the largest is 56th order requiring four devices while the smallest is 16th order requiring just one device. In order to accommodate multiplexing between high order polynomials (X 16th order) and lower order polynomials, a location of all zeros is provided. This allows the user to choose a lower order polynomial even if the system is configured for a higher order one. The 74F402 expandable CRC generator checker contains 6 popular CRC polynomials, 2-16th Order, 2-32nd Order, 148th Order and 1-56th Order. The application diagram shows the 74F402 connected for a 56th Order polynomial. Also shown are the input patterns for other polynomials. When the 74F402 is used with a gated clock, disabling the clock in a HIGH state will ensure no erroneous clocking occurs when the clock is re-enabled. Preset and Master Reset are asynchronous inputs presetting the register to S or clearing to 1s respectively (note Ethernet residue and 56th Order select code 8, LSB, are exceptions to this). To generate a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, data is applied to D input, output data is on D/CW. When the last data bit has been entered, CWG is set LOW and the register is clocked for n bits (where n is the order of the polynomial). The clock may now be stopped if desired (holding CWG LOW and clocking the register will output zeros from D/CW after the residue has been shifted out). To check a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, the data stream including the CRC is applied to D input. When the last bit of the CRC has been entered, the ER output is checked: HIGH = error free data, LOW = corrupt data. The clock may now be stopped if desired. To implement polynomials of lower order than 56th, select the number of packages required for the order of polynomial and apply the pattern for the selected polynomial to the S inputs (0000 on S inputs disables the package from the feedback chain).
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Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS IOHC ICC Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Open Collector, Output OFF Leakage Test Power Supply Current 110 -20 4.75 3.75 -0.4 -130 250 165 10% VCC 5% VCC 10% VCC 10% VCC 2.4 2.7 0.5 0.5 5.0 7.0 50 A A A V A mA mA A mA Max Max Max 0.0 0.0 Max Max Min Max Min 2.0 0.8 -1.2 Typ Max Units V V V V Min Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -5.7 mA (RO, D/CW) IOH = -5.7 mA (RO, D/CW) IOL = 16 mA (ER) IOL = 8 mA (D/CW, RO) VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 0V (D/CW, RO) VOUT = VCC (ER)
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AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPLH tPLH tPHL tPHL tPLH tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CP to D/CW Propagation Delay CP to RO Propagation Delay CP to ER Propagation Delay P to D/CW Propagation Delay P to RO Propagation Delay P to ER Propagation Delay MR to D/CW Propagation Delay MR to RO Propagation Delay MR to ER Propagation Delay D to D/CW Propagation Delay CWG to D/CW Propagation Delay Sn to D/CW 30 8.5 10.5 8.0 8.0 15.5 8.5 11.0 11.5 9.5 VCC = +5.0V CL = 50 pF Typ 45 15.0 18.0 13.5 14.0 26.0 14.5 18.5 19.5 16.0 19.0 23.0 17.0 18.0 33.0 18.5 23.5 24.5 20.5 Max TA = -55C to +125C VCC = +5.0V CL = 50 pF Min 30 7.5 9.5 7.0 7.0 14.0 7.5 10.0 10.5 8.5 26.5 26.5 26.0 22.5 38.5 23.5 31.0 32.0 31.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 30 7.5 9.5 7.0 7.0 14.0 7.5 10.0 10.5 8.5 21.0 25.0 19.0 20.0 35.0 20.5 25.5 26.5 22.5 Max MHz ns ns ns ns ns Units
10.0 10.5 11.0 9.0 16.5 6.0 7.5 6.5 7.0 11.5 9.5
17.0 18.0 19.0 15.5 28.0 10.5 12.0 11.0 12.0 19.5 16.0
21.5 23.0 24.0 19.5 35.5 13.5 16.0 14.0 15.5 24.5 20.0
9.0 9.5 10.0 8.0 14.5 5.0 6.5 5.5 6.0 9.0 8.5
26.0 29.0 28.5 23.5 39.0 19.5 20.0 21.5 21.5 29.0 25.0
9.0 9.5 10.0 8.0 14.5 5.0 6.5 5.5 6.0 10.5 8.5
23.5 25.5 26.0 21.5 37.5 15.0 18.0 15.5 17.5 26.5 22.0
ns ns ns ns ns ns ns
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74F402
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(H) tW(L) tREC tREC Setup Time, HIGH or LOW SEI to CP Hold Time, HIGH or LOW SEI to CP Setup Time, HIGH or LOW RFB to CP Hold Time, HIGH or LOW RFB to CP Setup Time, HIGH or LOW S1 to CP Hold Time, HIGH or LOW S1 to CP Setup Time, HIGH or LOW D to CP Hold Time, HIGH or LOW D to CP Setup Time, HIGH or LOW CWG to CP Hold Time, HIGH or LOW CWG to CP Clock Pulse Width HIGH or LOW MR Pulse Width, HIGH P Pulse Width, LOW Recovery Time MR to CP Recovery Time P to CP 4.5 4.5 0 0 11.0 11.0 0 0 13.5 13.0 0 0 9.0 9.0 0 0 7.0 5.5 0 0 4.0 4.0 4.0 4.0 3.0 5.0 Max TA = -55C to +125C VCC = +5.0V Min 6.0 6.0 1.0 1.0 14.0 14.0 0 0 16.0 15.5 0 0 11.5 11.5 0 0 9.0 8.0 0 0 7.0 5.0 7.0 5.0 4.0 6.5 Max TA = 0C to +70C VCC = +5.0V Min 5.0 5.0 0 0 12.5 12.5 0 0 15.0 14.5 0 0 10.0 10.0 0 0 8.0 6.5 0 0 4.5 4.5 4.5 4.5 3.5 ns 6.0 ns ns ns ns ns ns ns ns Max Units
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74F402 Serial Data Polynomial Generator/Checker
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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